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5. Design an 8-bit Adder/Subtractor with overflow detection using Full Adders. Assume the FA block is already available, so no need for a truth table and a k-map. Use the following 8-bit inputs \( \mathrm{A}=a_{7} a_{6} a_{5} a_{4} a_{3} a_{2} a_{1} a_{0}, \mathrm{~B}=b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0} \), where A and \( B \) are the numbers to be added or subtracted, and a one bit input \( M \) to indicate the mode (adder or subtractor). In the case of subtraction, use \( \mathrm{A} \) as the minuend and \( \mathrm{B} \) is the subtrahend. Use the following 8-bit output \( \mathrm{S}=S_{7} S_{6} S_{5} S_{4} S_{3} S_{2} S_{1} S_{0} \) to indicate the sum result, and the one-bit output \( C \) for the final carry out, and the one-bit output \( V \) for overflow. (30 points) In each of the following cases, determine the values of \( \mathrm{S}, \mathrm{C} \), and \( \mathrm{V} \) : a) \( \mathrm{M}=0, \mathrm{~A}=01110111, \mathrm{~B}=01100110 \) b) \( \mathrm{M}=0, \mathrm{~A}=10001000, \mathrm{~B}=10011001 \) c) \( \mathrm{M}=1, \mathrm{~A}=11001100, \mathrm{~B}=10001000 \) d) \( M=1, A=01010101, B=10101010 \) e) \( M=1, A=00000000, B=00010001 \)

The schematic diagram is : Adder/SubtractorSCVABM