(Solved): For the following questions, consider a four-stage pipelined Y86-64 processor with the following p ...

For the following questions, consider a four-stage pipelined Y86-64 processor with the following pipeline stages: - Fetch - Decode - Execute - Memory and Writeback And suppose it is executing the following: mrmovq $8(8\mathrm{r}8)$, org irmovq $\$1000$, t??? addq $6r9$, b $r$ b pushq s 88 subq os rsp, ofr 10 Question 1 (4 points) (see above) Suppose the processor used only stalling to resolve data hazards. In that case, if mrmovq is fetched during cycle 0 , subq would complete its memory and writeback stage during cycle Answer: Comments: Question 2 ( 6 points) (see above) Suppose the processor used forwarding (combined, when necessary, with stalling) to resolve data hazards. In that case, which of the following forwarding would be needed to execute the assembly snippet above without requiring additional stalling? Select all that apply. (It is possible that not all necessary forwarding is included as options below.) A. of o $r8$ from mrmovg to addq B. of \&rg from mrmovq to addq C. of \& 8 from irmovq to addq D. of $8\mathrm{r}8$ from addq to pushq E. of \& 8 from addq to subq F. of \&rsp from pushq to subq